1. Field of the Invention
A method for transmitting the system command of a computer system, more particularly, is provided for transmitting a power management command using a signal transmission protocol originally used for the system chips' communication, so the peripheral devices coupled with the system chips can enter a power mode smoothly.
2. Description of Related Art
The components and the peripherals of a computer system perform signal transmission via a bus transmitting digital data between each other. The bus, such as a peripheral component interconnect (PCI) bus, accelerated graphics port (AGP) or the like, is used for transmitting data. The signal or data transmission between a central processing unit (CPU) and a North/Southbridge chip or the system memory is through a specific bus, thereby both the peripherals and the system's components are coupled to the bus.
Reference is made to FIG. 1 showing the conventional. PCI bus 16 of a computer system that is used to couple with a plurality of peripheral devices a, b and c. In a low-power -mode of the computer system, a PCI special cycle performs when the CPU 10 receives a low-power instruction via the PCI bus 16 that is controlled by the Northbridge chip 11 or the Southbridge chip 12. After that, the peripheral devices a, b and c either enter a predetermined state in low-power-mode controlled by a BIOS (basic I/O system) 15, or transmit a low-power instruction to the system memory 13 or graphics chip 14 via a specific bus.
U.S. Pat. No. 6,357,013 discloses a plurality of low-power instructions transmitted via a PCI bus in a computer system. In view of the conventional PCI bus, every peripheral coupled to the PCI bus shares a 133 MB/sec bandwidth provided by a main channel for transmitting data to the Southbridge chip. Since the above-mentioned signal transmission via the PCI bus is set in timely order, if a large amount of data is being transmitted, the transmission rate will slower than normal. For example, if a new-development serial ATA (SATA) device or a gigabit-level network device couples to the conventional PCI bus, the efficiency of the transmission thereof will be reduced due to the insufficient amount of bandwidth.
As opposed to the current PCI standard using multi-drop technology, a PCI-Express standard introduces a switch point-to-point transmission technology. The physical layer of the PCI-Express bus has a set of single-tasking lane composed of a transmitting terminal and a receiving terminal. Moreover, each PCI-Express bus uses its own lane to independently communicate with the Southbridge chip. The common bus structure is few to use, rather an independent lane is used for the PCI-Express bus, thereby reducing interference within the data transmission. Furthermore, each piece of data under the PCI-Express standard has priority transmission, and therefore the PCI-Express standard will be the first chosen by the computer system.
The PCI-Express standard defines an L2 and L3 power mode used for supplying power to peripherals. Wherein, the L2 power mode indicates that a main power and a reference clock have been removed except for as auxiliary power. As such, the computer system enters its lowest power consuming condition and the system can be woken up anytime. The L3 power mode indicates that the main power and the reference clock have been removed without the provision of any auxiliary power and that the computer system will not resume until it reboots.
In the prior art, the power-saving mode of the computer system is initialized after some steps for signal communication between the CPU and the Southbridge chip, and the L2 and L3 power modes are defined. Then, an OS direct power management (OSPM) in the system initializes the peripheral devices to prepare to go into power-saving mode. Meanwhile, an advanced configuration and power interface (ACPI) installed in the Southbridge chip will notify the PCI-Express peripheral devices that they are prepared to go into power-saving mode.
Since the peripheral devices coupled to the Northbridge chip, such as a graphics card, a high-speed network card and the like, doesn't have any informing mechanism of a power mode command the peripheral devices coupled with the Northbridge chip via the PCI-Express bus will not enter a certain power mode smoothly.